FP ExplainersJul 07, 2022 10:45:52 IST
Artificial Intelligence and Machine Learning have been niche subjects with very limited implementations in mainstreaming computing and usage. That is mainly because users would need powerful computing systems to use them.
All that is likely to change thanks to the next generation of analogue computing chipsets which are set to become much more efficient and fast in terms of performance.
Thanks to a new design framework that a group of researchers has developed at the Indian Institute of Science, or IISc, we now have an analogue chipset called ARYABHAT-1, that will allow Artificial Intelligence and Machine Learning apps to perform much better and faster.
ARYABHAT-1 or the Analog Reconfigurable Technology and Bias-scalable Hardware for AI Tasks is especially helpful for AI-based applications which deal with object or speech recognition systems, like Alexa or Siri. They are also very useful in operations that require massive parallel computing at high speeds.
Most computing devices, be it your cellphones, laptops or desktop computers, use digital chips because the design process is simple and easily scalable. However, as Chetak Singh Thakur, an Assistant Professor at the Department of Electronic Systems Engineering (DESE), IISc explains, “The advantage of analogue is huge. You will get orders of magnitude improvement in power and size. In applications that don’t require precise calculations, analogue computing has the potential to outperform digital computing as the former is more energy-efficient.”.
Different machine learning architectures can be programmed on ARYABHAT and like most digital processors, it can operate robustly across a wide range of temperatures, the researchers say.
They add that the architecture is also “bias-scalable” that is, its performance remains the same when the operating conditions like voltage or current are modified. This means that the same chipset can be configured for either ultra-energy-efficient Internet of Things (IoT) applications or for high-speed tasks like object detection.
The design framework was developed as part of IISc student Pratik Kumar’s PhD work, and in collaboration with ShantanuChakrabartty, Professor at the McKelvey School of Engineering, Washington University in St Louis Washington University, US, who also serves as the university’s McDonnell Academy ambassador to IISc.
The researchers have outlined their findings in two pre-print studies that are currently under peer review. They have also filed patents and are planning to work with industry partners to commercialise the technology.
